SpMV 计算的 ARM 和 FPGA 异构加速器设计. (Chinese)

To address the problem of inefficient implementation of sparse matrix-vector multiplication (SpMV) at the edge, the authors study the storage format of sparse matrix and field programmable gate array( FPGA) acceleration method of SpMV and propose a multi-port modified compressed row format (MCSR) acceleration method combined with task-level data-level hardware optimization in ARM+FPGA architecture. Computational parallelism is improved by using multiple ports to access data in parallel. Parallel acceleration between and within loops is achieved using dataflow and pipeline. Fine-grained parallel caching and computation of data is achieved using array partition and stream transfer. The ARM+ FPGA architecture is used,with ARM completing the control of the system and offloading the computation to the FPGA for parallel acceleration. Experimental results show that the parallel acceleration optimized ARM+FPGA scheme can achieve up to 10 times acceleration compared with the single ARM scheme. And the increased resource consumption is within the acceptable range. The results also show that the larger the matrix size,the more non-zero value,the more obvious the acceleration effect. The research results are of practical value in the implementation of SpMV computing at the edge. [ABSTRACT FROM AUTHOR]

针对稀疏矩阵向量乘(Sparse Matrix-Vector Multiplication,SpMV)在边缘端实施效率不高的 问题,以稀疏矩阵的存储格式、SpMV 的现场可编程门阵列(Field Programmable Gate Array,FPGA)加 速为研究对象,提出了一种多端口改进的行压缩存储格式(Modified Compressed Sparse Row Format, MCSR)与 ARM+FPGA 架构任务级数据级硬件优化相结合的加速方法。 使用多个端口并行存取数 据来提高计算并行度;使用数据流、循环流水实现循环间、循环内的并行加速;使用数组分割、流传输 实现数据的细粒度并行缓存与计算;使用 ARM+FPGA 架构,ARM 完成对系统的控制,将计算卸载到 FPGA 并行加速。 实验结果表明,并行加速优化后的 ARM+FPGA 方案相较于单 ARM 方案最高可达 10 倍的加速效果,而且增加的资源消耗在可接受范围内,矩阵规模越大非零值越多加速效果越明 显。 研究成果在边缘端实施 SpMV 计算方面有一定实用价值。 [ABSTRACT FROM AUTHOR]

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