10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV VMIN Reduction With Negligible Active Power Overhead
In: IEEE Solid-State Circuits Letters, Jg. 4 (2021), S. 6-9
Online
academicJournal
Zugriff:
Titel: |
10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV VMIN Reduction With Negligible Active Power Overhead
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Autor/in / Beteiligte Person: | Guo, Z. ; Wiedemer, J. ; Kim, Y. ; Ramamoorthy, P.S. ; Sathyaprasad, P.B. ; Shridharan, S. ; Kim, D. ; Karl, E. |
Link: | |
Zeitschrift: | IEEE Solid-State Circuits Letters, Jg. 4 (2021), S. 6-9 |
Veröffentlichung: | 2021 |
Medientyp: | academicJournal |
ISSN: | 2573-9603 (print) |
DOI: | 10.1109/LSSC.2020.3044042 |
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