30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture
In: IEEE International Solid-State Circuits Conference (ISSCC); Jg. 64 (2021-02-13) S. 422-423
Online
Konferenz
Zugriff:
Titel: |
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture
|
---|---|
Autor/in / Beteiligte Person: | Park, Jae-Woo ; Kim, Doogon ; Ok, Sunghwa ; Park, Jaebeom ; Kwon, Taeheui ; Lee, Hyunsoo ; Lim, Sungmook ; Jung, Sun-Young ; Choi, Hyeongjin ; Kang, Taikyu ; Park, Gwan ; Yang, Chul-Woo ; Choi, Jeong-Gil ; Ko, Gwihan ; Shin, Jaehyeon ; Yang, Ingon ; Nam, Junghoon ; Sohn, Hyeokchan ; Hong, Seok-In ; Jeong, Yohan ; Choi, Sung-Wook ; Choi, Changwoon ; Shin, Hyun-Soo ; Lim, Junyoun ; Youn, Dongkyu ; Nam, Sanghyuk ; Lee, Juyeab ; Ahn, Myungkyu ; Lee, Hoseok ; Lee, Seungpil ; Park, Jongmin ; Gwon, Kichang ; Jeong, Woopyo ; Choi, Jungdal ; Kim, Jinkook ; Jin, Kyo-Won |
Link: | |
Quelle: | IEEE International Solid-State Circuits Conference (ISSCC); Jg. 64 (2021-02-13) S. 422-423 |
Veröffentlichung: | 2021 |
Medientyp: | Konferenz |
ISBN: | 978-1-7281-9549-0 (print) |
ISSN: | 2376-8606 (print) |
DOI: | 10.1109/ISSCC42613.2021.9365809 |
Sonstiges: |
|